Semiconductor integrated circuit device and manufacturing method thereof

ABSTRACT

An insulating film for protecting an upper portion of a control gate electrode is constituted by a silicon oxide film, and thereby stress affecting a gate oxide film and a substrate that is located below a bottom portion thereof is reduced. Further, an etching prevention film consisting of a silicon nitride film is formed on a sidewall of the silicon oxide film, and thereby it is possible to prevent the sidewall of the silicon oxide film from being etched in a hydrofluoric acid cleaning step after processing of a gate electrode.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor integrated circuitdevice and a manufacturing method thereof. The present inventionparticularly relates to a technique effectively applied to asemiconductor integrated circuit device including an electricallybatch-erasable and rewritable nonvolatile semiconductor memory device(flash memory).

In a manufacturing process of a semiconductor integrated circuit device,when silicon oxide films deposited on a semiconductor substrate areetched to form contact holes, a means is taken to prevent a lowersilicon oxide film exposed from each bottom portion of the contactholes, from being excessively etched. As the means, a technique isemployed in which a silicon nitride film is provided between an upperlayer and a lower layer of the silicon oxide films forming the contactholes, and only the upper layer of the silicon oxide films is etched byusing the silicon nitride film as an etching stopper (as disclosed in,for example, Japanese Patent Laid-Open No. 11-26574, etc).

Also, in a manufacturing process of a recent mass storage DRAM (DynamicRandom Access Memory), when contact holes for connecting bit lines andcapacitive elements to a semiconductor substrate are formed in spaces ofgate electrodes fined, a self align contact (SAC) technique is employed(as disclosed by, for example, Japanese Patent Laid-Open No. 9-252098,etc.). The SAC technique forms the contact holes to be self-aligned tothe spaces of the gate electrodes, by constituting an insulating film(referred to as a cap insulating film, a protection insulating film orthe like) covering upper portions of the gate electrodes and aninsulating film (sidewall insulating film) covering sidewalls of thegate electrodes by silicon nitride films, and by utilizing etching ratedifference between the silicon oxide films and the silicon nitridefilms.

Further, in recent years, the above-mentioned SAC technique hasgradually been employed in manufacturing processes of semiconductormemories other than the DRAM. For example, Japanese Patent Laid-Open No.10-289951 discloses an invention in which the SAC technique is appliedto a manufacturing process of an EEPROM (electrically erasableprogrammable read-only memory).

SUMMARY OF THE INVENTION

As a type among flash memories, there is known an NOR type flash memory.Each memory cell of the NOR type flash memory is provided between a gateoxide film and a control gate electrode (word line) located on an upperportion thereof, and is constituted by a so-called floating gate typeMISFET (Metal Insulator Semiconductor Field Effect Transistor) in whicha floating gate electrode electrically insulated from the peripherythereof is used as a charge accumulation region. A floating gate typeMISFET can relatively reduce a memory size since a control gateelectrode (word line) is laminated on an upper portion of a floatinggate electrode formed through a thin gate insulating film formed on amain surface of a semiconductor substrate. It can be, therefore, saidthat the floating gate type MISFET has a memory cell structure suitablefor realizing a mass storage.

In the case of the above-mentioned NOR type flash memory, there is atypical method for operation of being written into a memory cell. As thetypical method, electrons are injected into the floating gate electrode,and threshold voltage (Vth) of a transistor by using a control gateelectrode as a reference voltage is raised in comparison with a state inwhich no electrons thereof are accumulated. Injection of electrons intothe floating gate electrode has, as typical methods, two systems. Thereis one system in which, by changing a channel current flowing in asource and drain channel to hot electrons in the vicinity of a drain, anelectric field of the control gate electrode biased to have a positivevoltage makes the hot electrons drown into the floating gate electrode.As another example, there is the other system in which, by a positivevoltage applied to a control gate electrode, hot electrons generated byavalanche breakdown in the vicinity of a drain thereof are drown into afloating gate electrode. On the other hand, as a typical example of anerasing operation, there is utilized a system in which, by makingelectrons FN tunneling (Fowler-Nordheim tunneling) into a gateinsulating film below a floating gate electrode, the electrons which areaccumulated in the floating gate electrode, the electrons are dischargedinto the source or drain region of the semiconductor substrate.

Further, in the NOR type flash memory, memory cells are arranged in alattice shape at respective intersections between predetermined numberof word lines extending parallel to one direction and predeterminednumber of data lines extending parallel to a direction orthogonal tothese word lines, the data lines are connected to drain regions of aMISFET constituting each memory cell, and source lines are connected tosource regions thereof, respectively. Therefore, if each size of thememory cells is fined in order to make the NOR type flash memory massstorage, then the above-stated SAC technique is indispensable toformation of contact holes for connecting the data lines to the drainregions and that of contact holes for connecting the source lines to thesource regions.

However, in the case where the SAC technique is introduced into flashmemory manufacturing processes in order to form an insulating filmprotecting the upper portions of the control gate electrodes out of asilicon nitride film, a silicon nitride film over a control gateelectrode gives high stress to a gate oxide film and a substrate of alower portion thereof and causes crystal defects in the gate oxide film.As a result, it has become clear from consideration of the inventors ofthe present invention that there arises a problem peculiar to thefloating gate type MISFET, the problem being one that chargesaccumulated in the floating gate electrode easily leak into thesubstrate.

Taking this disadvantage into account, the inventors of the presentinvention has considered realization of micro-fabrication memory cellusing the SAC technique during suppression of the stress relative to thegate oxide film and the substrate of the lower portion thereof, byforming the protection insulating film over a control gate electrode bya silicon oxide film instead of a silicon nitride film or by alaminating film formed of a silicon oxide film and a silicon nitridefilm, and then by forming a sidewall insulating film by a siliconnitride film.

However, it has become clear that there arise the following problems ofa MISFET manufacturing process in the case of forming the protectioninsulating film over the control gate electrode by a silicon oxide film.These problems will be described with reference to FIGS. 45 to 50.

To form a MISFET having two-layer gate structure consisting of afloating gate electrode and a control gate electrode, first, apolycrystalline silicon film 102A, an ONO film 103, a polycrystallinesilicon film 104A, and a silicon oxide film 105 are sequentiallydeposited on a gate oxide film 101 formed on the main surface of asemiconductor substrate 100 in this order, as shown in FIG. 45. Thepolycrystalline silicon film 102A is used for a floating gate. The ONOfilm 103 consists of a silicon oxide film, a silicon nitride film and asilicon oxide film. The polycrystalline silicon film 104A is used for acontrol gate. The silicon oxide film 105 is served as a protectioninsulating film.

Next, as shown in FIG. 46, by using a photoresist film 106 as a mask,the silicon oxide film 105 is dry-etched. After the photoresist film 106is removed, as shown in FIG. 47, the polycrystalline silicon film 104A,the ONO film 103 and the polycrystalline silicon film 102A which arelocated below the silicon oxide film 105 are sequentially dry-etched byusing the silicon oxide film 105 as a mask. Thereby, floating gateelectrodes 102 consisting of the polycrystalline silicon film 102A areformed, and control gate electrodes 104 (word lines WL) consisting ofthe polycrystalline silicon film 104A are formed.

Next, as shown in FIG. 48, impurity ions are implanted into thesemiconductor substrate 100 corresponding to space regions between gateelectrodes (floating gate electrodes 102 and control gate electrodes104). Then, the semiconductor substrate 100 is heat-treated to diffusethe above-mentioned impurities, and thereby impurity introducing regions107 for constituting source regions and drain regions of the MISFET areformed.

Next, as shown in FIG. 49, the gate oxide film 101 is etched (wetcleaning) by using a hydrofluoric acid solution in order to removedamages generated on the gate oxide film 101 in the gate electrodeprocessing step and the ion implantation step as described above. Sincethe damages generated on the gate oxide film 101 become paths or thelike through which electrons injected into the floating gate electrodes102 leak from end portions of the floating gate electrodes 102 to thesemiconductor substrate 100, degradation of the gate oxide film 101 iscaused. It is, therefore, necessary to sufficiently remove the damagesby performing this etching (wet cleaning).

However, if the gate oxide film 101 is cleaned by using the hydrofluoricacid solution, the surfaces of the silicon oxide film 105 serving as aprotection insulating film which covers the upper portions of thecontrol gate electrodes 104 are also etched simultaneously along withthe gate oxide film 101. As a result, as shown in FIG. 49, respectivesidewalls of the silicon oxide film 105 retreat toward the centraldirections of the respective gate electrodes.

Due to this, as shown in FIG. 50, when a silicon nitride film 108serving as a sidewall insulating film is deposited on the semiconductorsubstrate 100 in the next step, stepped portions are generated on thesilicon nitride film 108 in the vicinity of respective boundariesbetween each control gate electrode 104 and the silicon oxide film 105.As a result, when contact holes are formed in the space regions of thegate electrodes (floating gate electrodes 102 and control gateelectrodes 104) by means of the SAC technique, the silicon nitride film108 on each stepped portion described above is removed and thicknessthereof becomes thin. Thereafter, a problem of defects has occurred suchthat a metal film embedded into each contact hole and the control gateelectrode 104 become closer to each other in the vicinity of eachstepped portion described above, and both become short-circuit accordingto circumstances. The problem like this arises even in the case wherethe protection insulating film covering the upper portion of eachcontrol gate electrode 104 is formed of a laminating film consisting ofa silicon oxide film and a silicon nitride film.

As stated above, by consideration of the inventors, it has become clearthat if a part of or all of the protection insulating film covering theupper portion of each control gate electrode is formed of a siliconoxide film in order to suppress stress of the gate oxide film and thesubstrate of the lower portion thereof, the stress being resulted fromthe silicon nitride film, then it is extremely difficult to realize themicro-fabrication of the MISFET by utilizing the SAC technique.

An object of the present invention is to provide a technique capable ofrealizing micro-fabrication of a MISFET using the SAC technique whilestress resulting from a silicon nitride film and affecting a gate oxidefilm and a substrate of the lower portion thereof is suppressed.

Another object of the present invention is to provide a techniquecapable of promoting realization of mass storage and micro-fabricationof a flash memory.

The above and other objects and novel features of the present inventionwill be apparent from the description of the present specification andthe accompanying drawings.

Of inventions disclosed by the present invention, typical embodimentsthereof will be described as follows.

According to one embodiment of the present invention, a semiconductorintegrated circuit device that is an object includes connection holes(contact holes) whose at least two sides are divided by at least onepair of laminating structure bodies that each are formed over a mainsurface of a semiconductor substrate to be adjacent to each other andthat each consist of a first electrode insulating film, a floating gateelectrode, a second gate insulating film, a control gate electrode and afirst protection insulating film which are laminated in this order. Theabove-mentioned first protection insulating film has an etchingprevention film at both sidewall portions thereof. When being in anetching step of said first gate insulating film along with theabove-mentioned first protection insulating film, this etchingprevention film is a substance that is difficult to etch in comparisonwith the first protection insulating film, that is, a substance that hasa different etching rate, or a substance that is in fact not etched.Preferably the above-mentioned first protection insulating film includesa silicon oxide film, and the above-mentioned etching prevention filmformed by the sidewall portions thereof is silicon nitride film.

In the case of forming, by a SAC technique, the contact holes in aninterlayer insulating film such as a silicon oxide film existing betweenone pair of laminating structure bodies mentioned above, a thin siliconnitride film for a side spacer is first formed along the entire surfacesof the laminating structure bodies, and the interlayer insulating filmis formed on the upper surface thereof so as to embed respective groovesbetween the laminating structure bodies. Then, relative to theinterlayer insulating film like this silicon oxide film, the siliconnitride film which is difficult to etch and which is a side spacerinsulating film becoming underlying, is used for etching as a stopperlayer (stopper). In this case, when a satisfactory thickness as theetching stopper layer can not be ensured over the side spacer siliconnitride film covering the above-mentioned first protection insulatingfilm, the first protection insulating film may be a laminating filmwhich laminates a silicon nitride film over an upper layer of a siliconoxide film so as to be capable of enduring etching amounts required toform the connection holes of the above-mentioned interlayer insulatingfilm. By doing so, the silicon nitride film of the above-mentioned firstprotection insulating film can be used as a part of the etching stopperlayer. According to the above-stated embodiment, it is possible to omitor reduce use of a protection insulating film material such as a siliconnitride material in which stress affects the semiconductor substratelaminated over the control gate electrode.

According to another embodiment that is the present invention, a methodfor manufacturing a semiconductor integrated circuit device including anMIS transistor structure on a main surface of a semiconductor substrateis an object, and is characterized by the steps of: forming a first gateinsulating film to cover an active region over the main surface of thesemiconductor substrate; forming at least one pair of laminatingstructure bodies which each comprises a floating gate electrode, asecond gate insulating film, a control gate electrode and a firstprotection insulating film which are laminated in this order;introducing impurities for forming a source or a drain through the firstgate insulating film exposed between said pair of laminating structurebodies; and removing or cleaning exposed portions of said first gateinsulating film given damages in the above-mentioned impurityintroduction step, wherein an etching prevention film is formed on thesidewall portions of said first protection insulating film in the stepof forming the above-mentioned laminating structure bodies so that thesidewall portions of said first protection insulating film is notretreated in the removing or cleaning step. In a preferable embodiment,the above-mentioned first protection insulating film may include asilicon oxide film, and, for the same reason stated above, may be alaminating film consisting of a silicon oxide film and a silicon nitridefilm. On the other hand, the above-mentioned etching prevention filmcovering the sidewall portions of the first protection insulating filmis a silicon nitride film. By so constitution, it is possible to omit orreduce use of a protection insulating film material such as a siliconnitride material in which stress thereof affects the semiconductorsubstrate laminated over the control gate electrode. Further, in thestep of removing or cleaning the exposed portion of the above-mentionedfirst gate insulating film, removing or cleaning of the first gateinsulating film exposed below the floating gate electrode can besatisfactorily carried on, in comparison with cleaning in a generaltransistor manufacturing step. Accordingly, in particular, since thedamaged parts of the first gate insulating film can be removed,characteristics of holding information written into a flash memory canbe improved.

According to still another embodiment that is the present invention, amethod for manufacturing a semiconductor integrated circuit devicehaving an MIS transistor structure of a flash memory includes the stepsof:

(a) forming, on a main surface of a semiconductor substrate, a firstgate insulating film consisting of a silicon oxide film, and forming afirst conductive film, a second gate insulating film and a secondconductive film over said first gate insulating film in this order;

(b) forming a first protection insulating film consisting of one of asingle layer film and a laminating film, said single layer film being asilicon oxide film formed over said second conductive film, and saidlaminating film being a silicon nitride film formed over the siliconoxide film;

(c) patterning said first protection insulating film, and therebyforming an etching mask consisting of said first protection insulatingfilm;

(d) patterning said second conductive film, said second gate insulatingfilm and said first conductive film in this order by dry etching usingsaid etching mask as a mask, and thereby forming a plurality of gateelectrodes that each have a floating gate electrode consisting of saidfirst conductive film and a control gate electrode consisting of saidsecond conductive film and that each have a laminating structure inwhich an upper portion of said control gate electrode is covered withsaid first protection insulating film;

(e) forming a etching prevention film consisting of a silicon nitridefilm on both sidewall portions of said first protection insulating filmpatterned, after said step (c) and before said step (d), or after saidstep (d);

(f) introducing impurities into the main surface of said semiconductorsubstrate located between sidewall portions facing each other in saidplurality of gate electrodes, and thereby forming a source region and adrain region;

(g) treating a surface of said semiconductor substrate by using etchantcontaining a hydrofluoric acid after said step (f), and thereby cleaningsaid first gate insulating film located between the sidewall portionswhich face each other in said plurality of gate insulating film;

(h) covering an upper portion and both sidewall portions of each of saidplurality of gate electrodes after said step (g), and forming a secondprotection insulating film consisting of a silicon nitride film havingsuch a thickness as to partially embed a region between the sidewallportions which face each other in said plurality of gate electrodes;

(i) forming, on an upper portion of said second protection insulatingfilm, an interlayer insulating film consisting of a silicon oxide film,and embedding, with said interlayer insulating film, the region betweenthe sidewall portions which face each other in said plurality of gateelectrodes;

(j) etching said interlayer insulating film and said second protectioninsulating film located between the sidewall portions which face eachother in said plurality of gate electrodes, and thereby forming a firstconnection hole for exposing a surface of said source region and asecond connection hole for exposing a surface of said drain region; and

(k) forming a third conductive film electrically connected to saidsource region inside said first connection hole, and forming a fourthconductive film electrically connected to said drain region inside saidsecond connection hole.

According to this embodiment, since the first protection insulating filmcovering the upper portion of the control gate electrode is constitutedby a silicon oxide film, it is possible to reduce stress which affectsthe first gate oxide film and the semiconductor substrate which islocated below a lower portion thereof, and to suppress generation ofcrystal defects in the first gate oxide film.

Further, since the etching prevention film consisting of a siliconnitride film is formed over both sidewall portions of the firstprotection insulating film consisting of the above-mentioned siliconoxide film, it is possible to prevent such drawbacks that the firstprotection insulating film is etched and retreated when the first gateinsulating film is cleaned by etchant containing a hydrofluoric acid.

Moreover, since the first protection insulating film is prevented fromretreating, the sidewall portions of the above-mentioned secondprotection insulating film is prevented from being unnecessarily etchedand thereby removed during processing of anisotropic etching of thesilicon nitride film which is the second protection insulating film. Asa result, as described above with reference to FIG. 50, it is possibleto prevent a disadvantage of decrease in withstand voltage between theconductive film being in contact with the drain region or the sourceregion and the control gate electrode, or a disadvantage ofshort-circuit between those conductors.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing principal parts of an NOR type flashmemory that is a first embodiment of the present invention.

FIG. 2 is a plan view showing principal parts of memory array in theflash memory that is the first embodiment of the present invention.

FIG. 3 is a cross-sectional view showing principal parts of asemiconductor substrate taken along line A—A in FIG. 2.

FIG. 4 is a cross-sectional view showing principal parts of thesemiconductor substrate taken along line B—B in FIG. 2.

FIG. 5 is an enlarged cross-sectional view of FIG. 4.

FIG. 6 is a plan view of principal parts showing a method formanufacturing a flash memory that is the first embodiment of the presentinvention.

FIG. 7 is a cross-sectional view of principal parts showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 8 is a cross-sectional view of principal parts showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 9 is a cross-sectional view of principal parts showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 10 is a cross-sectional view of principal parts showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 11 is a plan view of principal parts showing the method formanufacturing the flash memory that is the first embodiment of thepresent invention.

FIG. 12 is a cross-sectional view of principal parts showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 13 is a cross-sectional view of principal parts showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 14 is a cross-sectional view of principal parts showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 15 is a cross-sectional view of principal parts showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 16 is a cross-sectional view of principal parts showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 17 is a cross-sectional view of principal parts showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 18 is a cross-sectional view of principal parts showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 19 is a cross-sectional view of principal parts showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 20 is a cross-sectional view of principal parts showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 21 is a cross-sectional view of principal parts showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 22 is a cross-sectional view of principal parts showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 23 is a plan view of principal parts showing the method formanufacturing the flash memory that is the first embodiment of thepresent invention.

FIG. 24 is a cross-sectional view of principal parts. showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 25 is a cross-sectional view of principal parts showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 26 is a cross-sectional view of principal parts showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 27 is a cross-sectional view of principal parts showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 28 is an enlarged cross-sectional view of principal parts showingthe method for manufacturing a flash memory that is the first embodimentof the present invention.

FIG. 29 is a cross-sectional view of principal parts showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 30 is an enlarged cross-sectional view of principal parts showingthe method for manufacturing a flash memory that is the first embodimentof the present invention.

FIG. 31 is a cross-sectional view of principal parts showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 32 is a cross-sectional view of principal parts showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 33 is a cross-sectional view of principal parts showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 34 is a cross-sectional view of principal parts showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 35 is a plan view of principal parts showing the method formanufacturing a flash memory that is the first embodiment of the presentinvention.

FIG. 36 is a cross-sectional view of principal parts showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 37 is a cross-sectional view of principal parts showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 38 is a cross-sectional view of principal parts showing the methodfor manufacturing a flash memory that is the first embodiment of thepresent invention.

FIG. 39 is an enlarged cross-sectional view of principal parts showing aflash memory that is another embodiment of the present invention.

FIG. 40 is an enlarged cross-sectional view of principal parts showing aflash memory that is another embodiment of the present invention.

FIG. 41 is a cross-sectional view of principal parts showing a flashmemory that is another embodiment of the present invention.

FIG. 42 is a cross-sectional view of principal parts showing a flashmemory that is another embodiment of the present invention.

FIG. 43 is a schematic circuit diagram of an NAND type flash memory thatis another embodiment of the present invention.

FIG. 44 is a schematic circuit diagram of an AND type flash memory thatis another embodiment of the present invention.

FIG. 45 is a cross-sectional view for explaining problems that theinventors of the present invention have considered.

FIG. 46 is a cross-sectional view for explaining problems that theinventors of the present invention have considered.

FIG. 47 is a cross-sectional view for explaining problems that theinventors of the present invention have considered.

FIG. 48 is a cross-sectional view for explaining problems that theinventors of the present invention have considered.

FIG. 49 is an enlarged cross-sectional view for explaining problems thatthe inventors of the present invention have considered.

FIG. 50 is an enlarged cross-sectional view for explaining problems thatthe inventors of the present invention have considered.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will be described below in detailwith reference to the drawings. In all the drawings for describing theembodiments, members having the same function are denoted by the samereference numbers and repetitive description thereof will be omitted.

First Embodiment

FIG. 1 is a block diagram showing principal parts of a flash memory(electrically batch-erasable and rewritable nonvolatile semiconductormemory device) that is an embodiment of the present invention.

The flash memory is formed over a main surface of a semiconductor chipmade of monocrystalline silicon. The flash memory has a memory array(MARY) constituting storage sections, and peripheral circuit sectionsarranged around the memory array.

The memory array (MARY) has the predetermined number of word lines WL,the predetermined number of data lines DL, and many memory cells MC.Each of the word lines WL extends parallel to a right-and-left directionin FIG. 1. Each of the data lines DL extends parallel to an up-and-downdirection in FIG. 1. The memory cells MC are arranged in a lattice shapeat intersections between the word lines WL and the data lines DL,respectively. Each of the memory cells MC is constituted by a MISFEThaving a two-layer gate structure including a floating gate electrodeand a control gate electrode. The structure of this MISFET and amanufacturing method of the MISFET will be described later in detail.

The flash memory in this embodiment employs, for example, an NOR typememory array structure. The NOR type flash memory constitutes cell unitseach using, as a unit, the predetermined number (e.g., sixteen) ofmemory cells MC arranged on the same row. The control gate electrode ofeach of the memory cells MC constituting a cell unit is connected to acorresponding word line WL. Also, a drain region of each memory cell MCis connected to a corresponding data line DL and a source region thereofis connected to a source line SL extending in the up-and-down directionin FIG. 1.

The word lines WL are connected to an X address decoder XD and thesource lines SL are connected to a source voltage control circuit SVC.Also, the data lines DL are connected to an input/output circuit IOthrough a sense amplifier SA and a Y switch circuit YS.

The X address decoder XD is supplied with an internal X address signalfrom an X address buffer XB, with various internal control signals froma timing generation circuit TG, and with various internal voltages froma internal voltage generation circuit VG. Also, the source voltagecontrol circuit SVC is supplied with an internal Y address signal from aY address buffer YB, with various internal control signals from thetiming generation circuit TG, and with various internal voltages fromthe internal voltage generation circuit VG. Further, the Y switchcircuit YS is supplied with a data line select signal from the Y addressdecoder YD, and the Y address decoder YD is supplied with an internal Yaddress from the Y address buffer YB. The X address buffer XB issupplied with an X address signal from an external unit, and the Yaddress buffer YB is supplied with a Y address signal therefrom.

The X address buffer XB forms the internal X address signal on the basisof the X address signal supplied, and supplies the formed internal Xaddress signal to the X address decoder XD. The X address decoder XDdecodes the internal X address signal supplied from the X address bufferXB, and sets the word lines WL over the memory array (MARY) to be at aselect or unselect level.

On the other hand, the Y address buffer YB forms an internal Y addresssignal on the basis of the Y address signal supplied, and supplies theformed internal Y address signal to the source voltage control circuitSVC and to the Y address decoder YD. Also, the source voltage controlcircuit SVC decodes the internal Y address signal supplied from the Yaddress buffer YB, and sets the source lines SL on the memory array(MARY) to be at a select or unselect level. The Y address decorder YDdecodes the internal Y address signal supplied from the Y address bufferYB, and sets the data line select signal to be at a select levelrelative to the Y switch circuit YS. Further, the Y switch circuit YS isselectively connected between a corresponding circuit of the senseamplifier SA and the input/output circuit IO, in response to a highlevel of the data line select signal supplied from the Y address decoderYD.

The timing generation circuit TG selectively forms various internalcontrol signals on the basis of a chip enable signal (CEB), a writeenable signal (WEB) and an output enable signal (OEB) which are suppliedfrom the external unit as starting control signals, and supplies thevarious internal control signals to respective portions of the flashmemory. Also, the internal voltage generation circuit VG generatesvarious internal voltages on the basis of power source voltages (Vcc andVss) supplied from the external unit, and supplies the various internalvoltages to respective portions of the flash memory. The power sourcevoltage Vcc has a positive potential such as 3.3V. In addition, theinternal voltages generated by the internal voltage generation circuitVG include various potentials such as 10V, 3V or 1V necessary for write,erase or read operation.

FIG. 2 is a plan view of principal parts of the memory array (MARY)mentioned above. FIG. 3 is a cross-sectional view taken along line A—Ain FIG. 2. FIG. 4 is a cross-sectional view taken along line B—B in FIG.2. FIG. 5 is an enlarged cross-sectional view of FIG. 4.

A p-type well 4 is formed in a semiconductor substrate (referred to assubstrate hereinafter) 1 made of p-type single crystalline silicon. Manyactive regions L, whose circumferences are surrounded by elementisolation grooves 2, are formed in this p-type well 4. Each of theseactive regions L has a long band-like plane pattern extending parallelto a right-and-left direction in FIG. 2.

Many word lines WL extending parallel to the up-and-down direction inFIG. 2 and many data lines DL extending parallel to the right-and-leftdirection in FIG. 2, i.e., a direction orthogonal to the word lines WLare formed over the substrate 1 of the memory array (MARY). Many memorycells MC are arranged in a lattice shape at the intersections betweenthese word lines WL and data lines DL, respectively.

A MISFET constituting the above-mentioned memory cells MC includes agate oxide film (first gate insulating film) 6 formed on a surface ofthe p-type well 4, a floating gate electrode 7 formed on the gate oxidefilm 6, an ONO film (second gate insulating film) 8 formed on thefloating gate electrode 7, a control gate electrode 9 formed on the ONOfilm 8, and n-type impurity introduced regions (a source region and adrain region) 20 formed in the p-type well 4 at both sides of gateelectrodes (floating gate electrode 7 and control gate electrode 9).

The control gate electrode 9 of the above-mentioned MISFET constitutes aword line WL in a region other than the active region L. A data line DLis connected to one (drain region) of then-type impurity introducedregions 20 of the MISFET through each contact hole (connection hole) 27formed at each upper portion thereof, and a source line SL is connectedto the other region (source region) through each contact hole(connection hole) 28 formed at each upper portion thereof.

As shown in FIG. 5, a silicon oxide film (first protection insulatingfilm) 15 is formed on the control gate electrode 9 (word line WL) of theMISFET constituting each memory cell MC. An etching prevention film 17made of a silicon nitride film is formed on each sidewall of the siliconoxide film 15. The function of this etching prevention film 17 will bedescribed later. A silicon nitride film (second protection insulatingfilm) 22 is formed on the sidewall of the gate electrode (the floatinggate electrode 7 and the control gate electrode 9) and on an uppersurface of the silicon oxide film 15. This silicon nitride film 22, aswill be described later, is used to form each of the above-mentionedcontact holes 27 and 28 by a self alignment relative to the gateelectrode (floating gate electrode 7 and control gate electrode 9).

In write operation into the memory cell MC, a voltage of 6V is appliedto the drain region of the selected memory cell MC and a voltage of 9Vis applied to the control gate electrode 9 thereof while the sourceregion thereof and the well 4 are set to have a reference potential(zero potential). By doing so, a peak of electric field intensity isgenerated at an end portion of the drain region, a channel current ischanged to hot electrons (e⁻) in this drain region, and the hotelectrons are injected into the floating gate electrode 7 through thegate oxide film 6. Thereby, the write operation is executed.

In addition, in read operation, a voltage of 1V is applied to the drainregion of the selected memory cell MC and a voltage of 5V is applied tothe control gate electrode 9 thereof while the source region thereof andthe well 4 are set to have a reference potential(zero potential).Thereby, accumulation information is detected by detecting thepresence/absence of drain current flowing in the selected transistor. Onthe other hand, in erase operation, the drain regions and the wellregions of the memory cell MC are set to be in floating states, avoltage of 0V is applied to the control gate electrode 9 thereof, avoltage of 14V is applied to the source region thereof, and electronsaccumulated in the floating gate electrode 7 are discharged to a sourceregion side by FN tunneling of the gate oxide film 6. Therefore, theerase operation is executed.

Next, a manufacturing method of flash memory in this embodiment will bedescribed in the order of steps with reference to FIGS. 6 to 38. Amongthese figures, cross-sectional views each having a reference symbol A—Aare cross-sectional views taken along line A—A in FIG. 2 andcross-sectional views each having a reference symbol B—B arecross-sectional views taken along line B—B in FIG. 2.

First, as shown in FIG. 6 (which is a plan view showing principal partsof a memory array region) and FIG. 7, a plurality of element isolationgrooves 2 are formed in element isolation regions on the main surface ofthe substrate 1. Each of the element isolation grooves 2 is formed byetching the main surface of the substrate 1 to form a groove having adepth of about 250 nm, by depositing a silicon oxide film 3 having athickness of about 600 nm on the substrate 1 including the interior ofthis groove by a CVD method, and thereafter by polishing and removing,from the silicon oxide film 3, unnecessary portions outside the grooveby a chemical mechanical polishing or CMP method. As shown in FIG. 6, byforming these element isolation grooves 2, many active regions L eachhaving a long band-like plane pattern extending parallel to aright-and-left direction in FIG. 6 are formed over the substrate 1 ofthe memory array.

Next, as shown in FIG. 8, after p-type impurities, e.g., B (boron) ionsare implanted into the surface of the substrate 1, the substrate 1 issubjected to a heat treatment at a temperature of about 1000° C. todiffuse the p-type impurities into the substrate 1. Thereby, a p-typewell 4 is formed. Next, the substrate 1 is subjected to wet oxidation ata temperature of 800° C. to 900° C., and thereby a gate oxide film 6having a thickness of about 10 nm is formed on the surface of the p-typewell 4.

Next, as shown in FIG. 9 and FIG. 10, a polycrystalline silicon film 7Ahaving a thickness of about 70 nm to 100 nm is deposited over thesubstrate 1 by a CVD method. N-type impurities, e.g., phosphorus (P) aredoped into the polycrystalline silicon film 7A during the depositionstep. Alternatively, after an not doped polycrystalline silicon film 7Ais deposited, n-type impurities may be doped into the film 7A by an ionimplantation method. The polycrystalline silicon film 7A is used as thefloating gate electrode 7 of the MISFET constituting each memory cell.

Next, as shown in FIGS. 11, 12 and 13, the polycrystalline silicon film7A is subjected to dry etching using a photoresist film as a mask, andthereby a polycrystalline silicon film 7B having an long band-like planepattern extending along a direction of extension thereof is formed at anupper portion of the active region L.

Next, as shown in FIGS. 14 and 15, an ONO film 8 consisting of a siliconoxide film, a silicon nitride film and a silicon oxide film is formedover the substrate 1 over which the polycrystalline silicon film 7B hasformed. The ONO film 8 is used as the second gate insulating film of theMISFET constituting each memory cell. The ONO film 8 is formed by, forexample, sequentially depositing a silicon oxide film having a thicknessof 5 nm, a silicon nitride film having a thickness of 7 nm and a siliconoxide film having a thickness of 4 nm over the substrate 1 in this orderby a CVD method.

Then, as shown in FIGS. 16 and 17, a polycrystalline silicon film 9Ahaving a thickness of about 200 nm is formed on an upper portion of theONO film 8. Then, a silicon oxide film 15 having a thickness of about300 nm is formed on an upper portion of the polycrystalline silicon film9A. The polycrystalline silicon film 9A is deposited by a CVD method,and then n-type impurities are doped thereinto by an ion implantationmethod. The silicon oxide film 15 is deposited by a thermal CVD methodfor thermally decomposing, for example, tetraethoxy silane gas at atemperature of about 700° C. The polycrystalline silicon film 9A is usedas the control gate electrode 9 and the word line WL of the MISFETconstituting each memory cell. Also, the silicon oxide film 15 is usedas an insulating film for protecting an upper portion of the controlgate electrode 9.

As can be seen, in this embodiment, the insulating film for protectingthe upper portion of the control gate electrode 9 is constituted by thesilicon oxide film 15. Due to this, great stress does not occur in thegate oxide film 6 and the substrate 1 located at the lower portionthereof, differently from the case where this insulating film isconstituted by a silicon nitride film. As a result, it is possible tosuppress occurrence of crystal defects in the gate oxide film 6, andtherefore to realize high quality of the gate oxide film 6 in which thegeneration of leakage current is extremely little.

Next, as shown in FIG. 18, the silicon oxide film 15 is subjected to dryetching using a photoresist film 16 as a mask, and thereby a part of thepolycrystalline silicon film 9A is exposed. The silicon oxide film 15that has been subjected to dry etching has a long band-like planepattern extending in a direction orthogonal to a direction in which theactive region L extends.

Then, after the photoresist film 16 is removed, a thin silicon nitridefilm 17A having a thickness of about 15 nm to 30 nm is deposited overthe substrate 1 by a CVD method as shown in FIG. 19. Thereafter, asshown in FIG. 20, the silicon nitride film 17A is subjected toanisotropic dry etching to be left only on the sidewall of the siliconoxide film 15, and thereby a etching prevention film 17 formed of thesilicon nitride film 17A is formed on this sidewall.

Next, as shown in FIG. 21, by using, as a mask, the silicon oxide film15 having the etching prevention films 17 formed on the sidewallthereof, the polycrystalline silicon film 9A is subjected to dryetching. Then, as shown in FIG. 22, the ONO film 8 and thepolycrystalline silicon film 7B that are located below thepolycrystalline silicon film 9A are sequentially subjected to dryetching in this order. Thereby, the floating gate electrode 7 consistingof the polycrystalline silicon film 7B and the control gate electrode 9(word line WL) consisting of the polycrystalline silicon film 9A areformed, respectively. As shown in FIG. 23, each control gate electrode 9(word line WL) has a long band-like plane pattern extending in adirection (an up-and-down direction in FIG. 23) orthogonal to adirection in which each active region L extends.

Next, as shown in FIG. 24, to form the source region and the drainregion of the MISFET constituting each memory cell, n-type impurities(e.g., arsenic (AS)) are ion-implanted into the p-type well 4 located inthe space regions of the gate electrodes (floating gate electrode 7 andcontrol gate electrode 9). Thereafter, as shown in FIG. 25, in order tosuppress short channel effects of the MISFET constituting each memorycell, p-type impurities (boron (B)) are ion-implanted into the p-typewell 4 located in the above-mentioned space regions. Ion-implantation ofp-type impurities is performed in a wider region than a region in whichthe n-type impurities are implanted, by using an obliqueion-implantation method.

Next, as shown in FIG. 26, the substrate 1 is subjected to a heattreatment at a temperature of about 900° C. to diffuse the above-statedn-type impurities and p-type impurities into the p-type well 4. Thereby,n-type impurity introduced regions 20 each constituting the sourceregion and the drain region of the MISFET, and p-type impurityintroduced regions 21 for punch-through stoppers surrounding the n-typeimpurity introduced regions 20 are formed, respectively.

Through the steps executed so far, damages occurring in the processingstep of the gate electrode and the ion-implantation step of theimpurities remain on the gate oxide film 6 in the space regions of thegate electrodes (floating gate electrode 7 and control gate electrode9). The damages cause paths through which electrons injected into thefloating gate electrode 7 leak from the end portion of the floating gateelectrode 7 to the substrate 1, or the like. Thereby, quality of thegate oxide film 6 is degraded, so that it is necessary to sufficientlyremove the damages.

Considering this, as shown in FIG. 27, the gate oxide film 6 is etchedby using a hydrofluoric acid solution (HF:H₂O=1:99). To sufficientlyremove the damages caused in the gate oxide film 6, as shown in anenlarged view of FIG. 28, it is desirable to perform etching until thegate oxide film 6 (portions indicated by arrows) located under an endportion of the sidewall of the floating gate electrode 7 is retreated upto as much as at least a film thickness thereof.

As already stated above, in this embodiment, the etching prevention film17 consisting of a silicon nitride film is formed on the sidewall of thesilicon oxide film 15 which protects the upper portion of the controlgate electrode 9. Due to this, in the etching step of removing thedamages of the gate oxide film 6 as stated above, the sidewall of thesilicon oxide film 15 is etched, but is not retreated in a centraldirection of the gate electrode.

Next, as shown in FIGS. 29 and 30 (an enlarged view of FIG. 29), thesubstrate 1 is subjected to wet oxidation at a temperature of about 850°C. By doing so, a clean, non-damage and high quality gate oxide film 6having a thickness of about 10 nm is formed again on the space regionsof the gate electrodes (floating gate electrode 7 and control gateelectrode 9), i.e., on the surface of the n-type impurity introducedregions (source and drain regions) 20 and below end portions of thesidewall of the floating gate electrode 7.

Next, as shown in FIG. 31, a silicon nitride film 22 having a thicknessof about 130 nm is deposited over the substrate 1 by a CVD method, andthen a silicon oxide film 23 having a thickness of about 200 nm isdeposited at an upper portion of the silicon nitride film 22 by a CVDmethod. The thickness of the silicon nitride film 22 is set to be equalto or less than half the size of each space of the gate electrodes(floating gate electrode 7 and control gate electrode 9), such that eachspace region is not completely embedded in the silicon nitride film 22.On the other hand, the silicon oxide film 23 is deposited so as tocompletely embed this space region.

Next, as shown in FIG. 32, a silicon oxide film 24 having a thickness ofabout 800 nm is deposited on an upper portion of the silicon oxide film23 by a CVD method, and the silicon oxide film 24 is polished by a CMPmethod to flatten a surface thereof, and thereafter a silicon oxide film25 having a thickness of about 90 nm is deposited on an upper portion ofthe silicon oxide film 24 by a CVD method. The polishing and flatteningof the silicon nitride film 24 are performed to reduce differences inlevels between the memory array and the other regions (peripheralcircuit sections). Also, the silicon oxide film 25 is deposited to embedscratches generated on the surface of the silicon oxide film 24 duringthe above-stated polishing step.

Next, as shown in FIG. 33, by using, as a mask, a photoresist film 26formed on the upper portion of the silicon oxide film 25, the siliconoxide films 25, 24 and 23 in the space regions of the gate electrodes(floating gate electrode 7 and control gate electrode 9) are subjectedto dry etching. This etching is performed under the condition that theetching selectivity of silicon oxide to silicon nitride is increased.When a surface of the silicon nitride film 22 is exposed, the etchingoperation is stopped.

Next, as shown in FIG. 34, the silicon nitride film 22 and the thin gateoxide film 6, which is a lower layer thereof, in the space regions ofthe gate electrodes (floating gate electrode 7 and control gateelectrode 9) are subjected to dry etching, and thereby contact holes 27and 28 are formed in which the surfaces of the n-type impurityintroduced regions (source and drain regions) 20 are exposed. Thesilicon nitride film 22 is etched by an anisotropic etching method suchthat the silicon nitride film 22 remains on each sidewall of the gateelectrodes (floating gate electrode 7 and control gate electrode 9). Bydoing so, it is possible to form the contact holes 27 and 28 by aself-alignment relative to the gate electrodes (floating gate electrode7 and control gate electrode 9).

FIG. 35 shows a plane pattern of the contact holes 27 and 28. As shownin FIG. 35, each of the contact holes 27 formed on the upper portions ofone (drain region) of the n-type impurity introduced regions (source anddrain region) 20 has a hole-shaped pattern separated per active regionL. Namely, each of the contact holes 27 is formed at a rate of onebetween two MISFETs (memory cells MC) adjacent to each other in eachextending direction of the active regions L.

On the other hand, the contact holes 28 formed at the upper portions ofthe other region (source region) of the n-type impurity introducedregions (source and drain regions) 20 are arranged to have longband-like plane patterns extending along extending directions of thecontrol gate electrodes 9 (word lines WL). Namely, the contact holes 28are ones common to many MISFETs (memory cells MC) extending along theextending directions of the control gate electrodes 9 (word lines WL).

Next, as shown in FIG. 36, n-type impurities (P or As) are ion-implantedinto the n-type impurity introduced regions (source and drain regions)20 through the contact holes 27 and 28, and thereby the n-type impurityintroduced regions (source and drain regions) 20 are decreased inresistance. This ion implantation is performed in order to reduce eachcontact resistance between plugs 30 formed in the contact holes 27 and28 in a later step and the n-type impurity introduced regions (sourceand drain regions) 20.

Next, as shown in FIG. 37, the plugs 30 are formed in the contact holes27 and 28, respectively. To form the plugs 30, for example, a Ti filmhaving a thickness of about 10 nm and a TiN film having a thickness ofabout 80 nm are deposited on the silicon oxide film 25 and inside thecontact holes 27 and 28 by a sputtering method. Subsequently, a W filmhaving a thickness of about 350 nm is deposited on an upper portion ofthe TiN film by a CVD method. Thereafter, the Ti film, the TiN film andthe W film outside the contact holes 27 and 28 are removed by a CMPmethod. The plugs 30 formed in the contact holes 28 located on upperportions of the source regions constitute source lines SL common to manyMISFETs (memory cells MC) along the extending directions of the controlgate electrodes 9 (word lines WL).

Next, as shown in FIG. 38, after a silicon oxide film 31 having athickness of about 30 nm is deposited on the upper portion of thesilicon oxide film 25 by a CVD method, silicon oxide film 31 on theupper portions of the contact holes 27 is removed by dry etching using aphotoresist film as a mask, and thereby through holes 32 are formed toexpose each surface of the plugs 30.

Thereafter, a W film having a thickness of about 350 nm is deposited onthe silicon oxide film 31 and inside the through holes 32 by asputtering method and a CVD method. Subsequently, the W film ispatterned by dry etching using a photoresist film as a mask to form datalines (DL), and thereby the memory cells MC shown in FIGS. 2 to 4 arenearly completed. Then, Al (Aluminum) wirings composed of about twolayers are formed on upper portions of the data lines (DL) through aninterlayer insulating film, but each figure of the Al wirings isomitted.

According to the present embodiment, it is possible to achieve fineprocessing using the SAC technology without degeneration ofcharacteristics of the MISFET constituting each memory cell MC. Thereby,it is possible to promote mass storage and a fine structure of each NORtype flash memory.

(Second Embodiment)

In the first embodiment mentioned above, the insulating film whichprotects the upper portion of each control gate electrode 9 isconstituted only by the silicon oxide film 15 in order to suppressgeneration of crystal defects in the gate oxide film 6 of the MISFETconstituting each memory cell MC. In this embodiment, as shown in FIG.39, a protection insulating film on each control gate electrode 9 isconstituted by a silicon oxide film 15 and a silicon nitride film 18deposited on each upper portion thereof.

By constituting so, it is possible to achieve fine structure of eachmemory cell MC in size and to reduce respective spaces between theadjacent memory cells MC. Therefore, as shown in FIG. 40, even if eachradius of the contact holes 27 (28) is relatively larger than eachspace, it is possible to prevent such drawbacks that the silicon oxidefilm 15 on each control gate electrode 9 is deeply cut by etching whenthe contact holes 27 (28) are formed. Even in this case, it is desiredto minimize a film thickness of the silicon nitride film 18 in order tosuppress generation of crystal defects in the gate oxide film 6.

Further, even in this case, since an etching prevention film 17 composedof a silicon nitride film is formed on each sidewall of a protectioninsulating film (silicon oxide film 15 and silicon nitride film 18), itis possible to prevent such drawbacks that the sidewall of the siliconoxide film 15 is etched by the hydrofluoric acid cleaning step mentionedabove and is thereby retreated.

Furthermore, in the first embodiment described above, as shown in FIGS.18 to 22, the silicon oxide film 15 is subjected to dry etching toexpose parts of the polycrystalline silicon film 9A. Thereafter, theetching prevention film 17 is formed on each sidewall of the siliconoxide film 15. Then, the silicon oxide film 15, on each sidewall ofwhich the etching prevention film 17 is formed, is used as a mask toperform sequentially dry etching of the polycrystalline silicon film 9A,the ONO film 8 and the polycrystalline silicon film 7B. On the otherhand, as shown in FIGS. 41 and 42, the silicon oxide film 15 is used asa mask to perform dry etching of the polycrystalline silicon film 9A,the ONO film 8 and the polycrystalline silicon film 7B, and thereafterthe etching prevention film 17 may be formed on each sidewall thereof.Even in this case, it is possible to prevent such drawbacks that thesidewall of the silicon oxide film 15 is etched by the above-mentionedhydrofluoric acid cleaning step and is retreated.

As described above, the inventions made by the present inventors havebeen concretely described on the basis of the above-mentionsembodiments. However, needless to say, the present invention is notlimited to the above-mentioned embodiments and various changes andmodifications thereof may be made without departing from the gistthereof.

In the above-mentioned embodiments, description has been given to thecase where the present invention is applied to the NOR type flashmemory. However, the present invention is not limited to the NOR typeflash memory. For example, the present invention is also applicable toother flash memory constituting each memory cell formed by a MISFEThaving a two-layer gate structure of a floating gate electrode and acontrol gate electrode. Namely, as shown in FIG. 43, the presentinvention can be applied to the case where each contact hole 40connecting a drain region of each selected MISFET (BDS) of an NAND typeflash memory to each data line DL is formed in a self-aligned manner.Or, as shown in FIG. 44, the present invention can be applied to thecase where each contact hole 41 connecting a drain region of eachselected MISFET (BDS) of an AND type flash memory to each data line DLis formed in a self-aligned manner. Thereby, it is possible to promotemass storages and fine structures of each NAND type flash memory andeach AND type flash memory.

Of inventions disclosed by the present application, effects obtained bythe typical inventions will be briefly described as follows.

According to the present invention, it is possible to achieverealization of fine processing using the SAC technique withoutdegeneration of characteristics of the MISFET constituting each memorycell.

According to the present invention, it is possible to promote massstorage and a fine structure of the flash memory.

What is claimed is:
 1. A method for manufacturing a semiconductorintegrated circuit device including a MIS transistor structure, themethod comprising the steps of: (a) forming a first gate insulating filmfor forming the MIS transistor structure on a main surface of asemiconductor substrate; (b) forming at least one pair of laminatedstructure bodies each including two layers of a first gate electrodecovering a part of said first gate insulating film and a firstinsulating film covering said first gate electrode, an etchingprevention film being formed on a sidewall portion of said firstinsulating film but so as not to cover sidewall portions of said firstgate electrode; (c) introducing impurities into said semiconductorsubstrate through said first gate insulating film located in a regionnot covered with said laminated structure bodies, and thereby forming afirst impurity introduced region self-aligned with said laminatedstructure bodies on the main surface of said semiconductor substrate;(d) removing said first gate insulating film in the region not coveredwith said laminated structure bodies after said step (c); and (e)forming a second insulating film covering upper portions and sidewallportions of said laminated structure bodies after said step (d).
 2. Themethod for manufacturing a semiconductor integrated circuit deviceaccording to claim 1, further comprising a step of: (d-2) oxidizing themain surface of said semiconductor substrate in a region from which saidfirst gate insulating film is removed, and thereby forming an insulatingfilm on said main surface, between said steps (d) and (e).
 3. The methodfor manufacturing a semiconductor integrated circuit device according toclaim 2, further comprising the steps of: (f) forming a third insulatingfilm over said second insulating film so as to cover said laminatedstructure bodies covered with said second insulating film and to embedeach space between said laminated structure bodies; and (g) forming amask for a contact hole over said third insulating film, and selectivelyremoving said third insulating film and said second insulating film in alaminating direction thereof by anisotropic etching using said mask, andthereby forming the contact hole which penetrates said third insulatingfilm and said second insulating film and which reaches a surface of saidfirst impurity introduced region.
 4. The method for manufacturing asemiconductor integrated circuit device according to claim 3, furthercomprising a step of: (h) forming a wiring conductive layer embeddingsaid contact hole and electrically connected to said first impurityintroduced region, after said step (g).
 5. The method for manufacturinga semiconductor integrated circuit device according to claim 4, whereina second gate insulating film and a second gate electrode laminated onan upper portion thereof are interposed between said first gateelectrode and said first insulating film of each of said laminatedstructure bodies.
 6. The method for manufacturing a semiconductorintegrated circuit device according to claim 4, wherein said firstinsulating film includes a silicon oxide film, said first gateinsulating film and said third insulating film each include a siliconoxide film, and said etching prevention film and said second insulatingfilm each include a silicon nitride film.
 7. The method formanufacturing a semiconductor integrated circuit device according toclaim 6, wherein said first gate electrode and said second gateelectrode consist of a polycrystalline silicon film, and said secondgate insulating film consists of a three-layer film in which a siliconoxide film, a silicon nitride film and a silicon oxide film arelaminated in this order.
 8. The method for manufacturing a semiconductorintegrated circuit device according to claim 7, wherein said firstinsulating film consists of a two-layer film in which a silicon oxidefilm and a silicon nitride film are laminated in this order, and saidetching prevention film is formed to cover a sidewall portion of saidtwo-layer film.
 9. A method for manufacturing a semiconductor integratedcircuit device, comprising the steps of: (a) forming, on a main surfaceof a semiconductor substrate, a first gate insulating film consisting ofa silicon oxide film, and forming a first conductive film, a second gateinsulating film and a second conductive film over said first gateinsulating film in this order: (b) forming a first protection insulatingfilm consisting of a single layer silicon oxide film formed over saidsecond conductive film, with or without a laminating silicon nitridefilm formed over the silicon oxide film; (c) patterning said firstprotection insulating film, and thereby forming an etching maskconsisting of said first protection insulating film; (d) patterning saidsecond conductive film, said second gate insulating film and said firstconductive film in this order by dry etching using said etching mask asa mask, and thereby forming a plurality of gate electrodes that eachhave a floating gate electrode formed by a portion of said firstconductive film and a control gate electrode formed by a portion of saidsecond conductive film and that each have a laminated structure in whichan upper portion of said control gate electrode is covered with saidfirst protection insulating film; (e) forming an etching prevention filmconsisting of a silicon nitride film on the patterned first protectioninsulating film, after said step (c) and before said step (d), or aftersaid step (d), said etching prevention film being formed on bothsidewall portions of the patterned first protection insulating film butso as not to cover sidewall portions of said floating gate electrode andsaid control gate electrode formed in said step (d); (f) introducingimpurities into the main surface of said semiconductor substrate locatedbetween sidewall portions facing each other in said plurality of gateelectrodes, and thereby forming a source region and a drain region; (g)treating a surface of said semiconductor substrate by using etchantcontaining a hydrofluoric acid after said step (f), and thereby cleaningsaid first gate insulating film located between the sidewall portionswhich face each other in said plurality of gate electrodes; (h) coveringan upper portion and both sidewall portions of each of said plurality ofgate electrodes after said step (g), and forming a second protectioninsulating film consisting of a silicon nitride film having such athickness as to partially embed a region between the sidewall portionswhich face each other in said plurality of gate electrodes; (i) forming,on an upper portion of said second protection insulating film, aninterlayer insulating film consisting of a silicon oxide film, andembedding, with said interlayer insulating film, the region between thesidewall portions which face each other in said plurality of gateelectrodes; (j) etching said interlayer insulating film and said secondprotection insulating film located between the sidewall portions whichface each other in said plurality of gate electrodes, and therebyforming a first connection hole for exposing a surface of said sourceregion and a second connection hole for exposing a surface of said drainregion; and (k) forming a third conductive film electrically connectedto said source region inside said first connection hole, and forming afourth conductive film electrically connected to said drain regioninside said second connection hole.
 10. The method for manufacturing asemiconductor integrated circuit device according to claim 9, whereinsaid third conductive film formed inside said first connection holefunctions as a part of a source line, and said fourth conductive filmformed inside said second connection hole functions as a part of a dataline.
 11. The method for manufacturing a semiconductor integratedcircuit device according to claim 10, wherein each of said plurality ofgate electrodes constitutes part of a respective memory cell of a flashmemory, and writing into said memory cell is carried out by injecting acharge into said floating gate electrode thereof, and erasing from saidmemory cell is carried out by discharging, to said semiconductorsubstrate, said charge injected into said floating gate electrodethereof.
 12. The method for manufacturing a semiconductor integratedcircuit device according to claim 7, wherein said flash memory is an NORtype flash memory.
 13. The method for manufacturing a semiconductorintegrated circuit device according to claim 1, wherein each of said atleast one pair of laminated structure bodies constitutes a memory cellof a flash memory, and writing into said memory cell is carried out byinjecting a charge into said floating gate electrode.
 14. The method formanufacturing a semiconductor integrated circuit device according toclaim 13, wherein said flash memory is an NOR type flash memory.
 15. Themethod for manufacturing a semiconductor integrated circuit deviceaccording to claim 9, wherein said step (g) is conducted so that saidfirst gate insulating film retreats beneath opposite sidewall portionsof said floating gate electrode.
 16. A method for manufacturing asemiconductor integrated circuit device having an MIS transistorstructure of a flash memory, comprising the steps of: (a) forming, on amain surface of a semiconductor substrate, a first gate insulating film,and forming a first conductive film, a second gate insulating film and asecond conductive film over said first gate insulating film in thisorder; (b) forming a first protection insulating film consisting of asingle layer silicon oxide film formed over said second conductive film,with or without a laminating silicon nitride film formed over thesilicon oxide film; (c) patterning said first protection insulatingfilm, and thereby forming an etching mask consisting of said firstprotection insulating film; (d) patterning said second conductive film,said second gate insulating film and said first conductive film in thisorder by dry etching using said etching mask as a mask, and therebyforming a plurality of gate electrodes that each have a floating gateelectrode formed by a portion of said first conductive film and acontrol gate electrode formed by a portion of said second conductivefilm and that each have a laminated structure in which an upper portionof said control gate electrode is covered with said first protectioninsulating film; (e) forming an etching prevention film consisting of asilicon nitride film on the patterned first protection insulating film,after said step (c) and before said step (d), or after said step (d),said etching prevention film being formed on both sidewall portions ofthe patterned first protection insulating film but so as not to coversidewall portions of said floating gate electrode and said control gateelectrode formed in said step (d); (f) introducing impurities into themain surface of said semiconductor substrate located between sidewallportions facing each other in said plurality of gate electrodes, andthereby forming a source region and a drain region; (g) treating asurface of said semiconductor substrate by using etchant after said step(f); (h) covering an upper portion and both sidewall portions of each ofsaid plurality of gate electrodes after said step (g), and forming asecond protection insulating film consisting of a silicon nitride filmhaving such a thickness, as to partially embed a region between thesidewall portions which face each other in said plurality of gateelectrodes; (i) forming, on an upper portion of said second protectioninsulating film, an interlayer insulating film consisting of a siliconoxide film, and embedding, with said interlayer insulating film, theregion between the sidewall portions which face each other in saidplurality of gate electrodes; (j) etching said interlayer insulatingfilm and said second protection insulating film located between thesidewall portions which face each other in said plurality of gateelectrodes, and thereby forming a first connection hole for exposing asurface of said source region and a second connection hole for exposinga surface of said drain region.
 17. The method for manufacturing asemiconductor integrated circuit device according to claim 16, furthercomprising the steps of: forming a third conductive film electricallyconnected to said source region inside said first connection hole, andforming a fourth conductive film electrically connected to said drainregion inside said second connection hole.
 18. The method formanufacturing a semiconductor integrated circuit device according toclaim 17, wherein said third conductive film formed inside said firstconnection hole functions as a part of a source line, and said fourthconductive film formed inside said second connection hole functions as apart of a data line.
 19. The method for manufacturing a semiconductorintegrated circuit device according to claim 18, wherein each of saidplurality of gate electrodes constitutes part of a respective memorycell of a flash memory, and writing into said memory cell is carried outby injecting a charge into said floating gate electrode thereof, anderasing from said memory cell is carried out by discharging, to saidsemiconductor substrate, said charge injected into said floating gateelectrode thereof.
 20. The method for manufacturing a semiconductorintegrated circuit device according to claim 16, wherein said flashmemory is a NOR type flash memory.
 21. The method for manufacturing asemiconductor integrated circuit device according to claim 16, whereinsaid step (g) is conducted so that said first gate insulating filmretreats beneath opposite sidewall portions of said floating gateelectrode.
 22. The method for manufacturing a semiconductor integratedcircuit device according to claim 1, wherein said step (d) is conductedsuch that said first gate insulating film retreats beneath oppositesidewall portions of said first gate electrode.